1. Field of the Invention
The present invention relates to a loop filter circuit for providing fast acquisition in a phase locked loop (PLL) utilizing a phase detector which generates voltage spikes during the locked state of PLL operation.
2. Description of the Prior Art
A phase locked loop (PLL) is a feedback system typically comprising, a phase detector or phase comparator, a "loop filter," and a voltage controlled oscillator (VCO). The loop filter typically comprises a low pass filter. The VCO output signal is applied to one input terminal of the phase comparator, the other input terminal of the phase comparator being receptive of an input reference signal. The phase comparator generates an error signal, indicative of phase differences between the VCO output signal and the reference signal. The error signal is applied to the loop filter, the output signals of the loop filter being, in turn, applied to the control input of the VCO. Thus, the feedback of the error signal causes the oscillator frequency to approach more closely and eventually lock onto the phase of the reference input signal.
A phase locked loop has three operational modes or states: a free running state, wherein no reference signal is applied to the phase comparator; a capture or acquisition state wherein the VCO output signal is different from the reference signal and the VCO is in the process of continually changing output signal phase until the VCO output signal maintains the same phase as the reference signal; and a locked state wherein the VCO output signal tracks and varies exactly with the phase of the reference signal.
For a more detailed description of phase locked loop circuits and operation, reference is made to "Phase Lock Techniques" by Floyd Gardner, N.Y., Wiley and Sons, 1966.
The transfer function of a phase locked loop is defined as the phase of the VCO signal divided by the phase of the reference signal, and is determined, to a large extent, by the transfer function of the loop filter. Accordingly, the "loop bandwidth," defined as the 3 db frequency range of the loop transfer function, is also primarily controlled by the parameters of the loop filter.
An engineering dilemma arises with respect to the loop bandwidth in that, in many applications of PLL's, the criteria for the loop bandwidth is different for the various modes of operation. For example, in some instances, the loop bandwidth should be made as narrow as possible to minimize phase jitter in the VCO output signal, such phase jitter being caused by external noise present in the reference signal, and yet the loop bandwidth should be made as wide as possible to maintain good tracking and acquisition properties.
For example, such an engineering dilemma rises when a phase locked loop is utilized to perform the function of a band pass filter. Computer aided ranging systems often utilize phase locked loops in such a manner. It is desirable in such systems, in order to conserve computer time, that the PLL acquire a signal as quickly as possible. Accordingly, during the acquisition mode of operation, the time constant of the PLL loop filter must be as short as possible and the bandwidth, therefore, as wide, as possible. However, for the PLL to perform properly the function of a bandpass fiter, a predetermined loop bandwidth, typically less than that desirable during the acquisition mode, must be maintained during the locked state.
The approach in the prior art to such loop bandwidth dilemmas has been to utilize a "passive loop filter" comprising first and second resistors and a capacitor, serially connected between the input terminal of the loop filter and ground. Two oppositely poled diodes are connected in parallel across the first resistor. The output signal of the phase comparator is applied to the first resistor and the output of the loop filter is taken across the second resistor and capacitor. During the acquisition mode a differential voltage exists across the diodes and current flows through the diodes. The first resistor is thus bypassed and, in effect, removed from the filter. When phase lock is reached, an equipotential exists across the diodes, and the diodes accordingly become non-conductive. The first resistor is thereby made a factor in determining the time constant of the filter. Thus, during the locked state, the PLL maintains a predetermined narrow bandwidth and, during the acquisition state when the first resistor is not a factor in determining the loop filter time constant, the loop bandwidth is broadened to achieve thus faster acquisition.
The immediately above described "passive loop filter," hereinafter referred to as the "prior art solution loop filter," is not suitable for use in various types of PLL's. For example, it is desirable to have a PLL which locks on frequency as well as phase, and that will not falsely "lock" onto input reference signals that are close to harmonics of the VCO center frequency. Such a PLL is available in integrated circuit form, for example, in a COS/MOS micropower digital integrated circuit, RCA-CD 4046A. The integrated circuit includes a frequency-sensitive phase-comparator, termed an "edge-controlled digital memory network," comprising four flip-flop stages, control logic circuitry and a three-state output circuit. Such a frequency-sensitive phase comparator provides a positive or negative voltage output signal, in accordance with the sense (direction) of frequency displacement of the VCO output signal from the reference signal. Where the frequencies of the VCO output and reference signals are the same, but the signals are out of phase, the phase comparator generates output pulses having a polarity in accordance with the lead or lag of the VCO signal with respect to the reference, the duration or width of the pulses being indicative of the magnitude of the phase difference. The output impedance of the phase comparator during the generation of such output signals is essentially zero. When phase lock between the VCO output and reference signals is achieved the phase comparator produces an output signal at ground potential (typically zero volts) and maintains essentially infinite resistance, i.e. appears as a virtual open circuit.
The loop filter circuit, typically an R-C low pass filter, in effect, integrates the pulses to convert the pulses to a DC signal, i.e., the filter capacitor is charged by the pulses. The D.C. signal is applied to the control terminal of the VCO to adjust thereby the VCO output frequency. When both the frequency and phase of the VCO output and reference signals are the same, the essentially infinite output resistance of the phase comparator maintains the voltage on the filter capacitor at the "equilibrium" value. For a more detailed description of such a phase comparator, reference is made to the data sheet for the aforementioned RCA-CD 4046A, which may be found at file No. 637 of the "RCA Solid State Databook" on COS/MOS Digital Integrated Circuits.
It is noted, however, that the output impedance of the comparator is not actually infinite and that a small leakage current exists, causing a slight decay of the capacitor voltage. Further, small leakages exist at the VCO input terminal and in the capacitor itself. Such leakage current causes a slight variation of the VCO output signal from the reference signal. Accordingly, during the locked state, the comparator continually generates spurious bipolar impulse-like voltage spikes.
The above described prior art solution loop filter is not suitable for use in a PLL utilizing a comparator, such as described above, which generates voltage spikes during the locked state of operation. The diode arrangement of the prior art solution loop filter would couple the voltage spikes directly to the VCO. Such coupling is undesirable in that the voltage spikes would cause modulation of the VCO output signal, which would appear as phase jitter, occurring at a rate equal to the reference frequency, on the VCO output signal. Where the VCO output signal is at the same frequency as the reference signal, the effect of such phase jitter would be an undesirable distortion of the VCO output signal waveform.